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Crossword: Processer Management

Across

1. The process of discarding all instructions in a pipeline due to a misprediction or hazard, and restarting the pipeline.

2. The sequence in which tasks or processes are actually executed by the system.

3. A technology that allows a single processor core to execute multiple threads simultaneously, improving efficiency.

4. The total time a process spends waiting in the ready queue before being executed.

5. The time at which a process enters the system and is ready to be executed by the CPU.

6. A series of stages through which instructions pass in a processor pipeline, each stage carrying out a specific operation.

7. The process of saving and restoring the state of a process when it is interrupted for execution by another process.

8. The amount of time a process requires to complete its execution without any interruption.

9. The ability of different parts of a program to be executed out of order or in partial order without affecting the final outcome.

10. A situation where two or more competing actions are waiting for the other to finish, preventing any of them from completing.

11. The time it takes for a processor to respond to a command or input.

12. The total time taken by a process from arriving in the system to its completion.

13. A type of scheduling where a task can be interrupted and moved out of the CPU before it has completed its execution.

14. A signal sent by a hardware device to request attention from the CPU by causing an interrupt to be processed.

Down

15. The process of comparing the performance of a processor against standard reference points or other processors.

16. A small, high-speed memory storage unit that temporarily holds frequently accessed data and instructions for faster processing.

17. A method used to determine the order in which processes are executed by the CPU based on certain criteria such as priority, fairness, and efficiency.

18. A memory address pointer pointing to the location of the interrupt service routine that needs to be executed when an interrupt occurs.


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