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1. A condition in processor pipelining where the next instruction cannot execute in the next stage due to a dependency or conflict.
2. A condition in processor pipelining where the hardware is unable to support overlapping of certain stages.
3. A series of stages through which instructions pass in a processor pipeline, each stage carrying out a specific operation.
4. The process of discarding all instructions in a pipeline due to a misprediction or hazard, and restarting the pipeline.
5. A technique in computer architecture that allows multiple instruction stages to be overlapped in order to improve efficiency and performance.
6. A type of pipeline hazard where a later instruction depends on the result of an earlier instruction that has not yet completed.